1. Field of the Invention
The present invention relates to a digitally-controlled power supply controller and power supply control method, and relates in particular to control technology for an A/D (analog/digital) converter for digitally controlled power supplies.
2. Description of Related Art
In recent years, digitally controlled power supply controllers are being utilized to extend the operating time of mobile devices such as cellular telephones that have become widely used. In digitally controlled power supply controllers, an A/D converter carries out sampling to sample the output voltage. Sampling with a high-resolution A/D converter must be performed in order to suppress fluctuations in the output voltage. In digitally controlled power supply controllers have problems with high-speed startups and regulating the startup speed of the supply voltage when switching between applications using different voltages.
FIG. 7 is a block diagram of the A/D converter of a related art described in Japanese Patent Application Laid Open No. 2006-140819.
An A/D converter 1 contains a sample hold circuit 3, a D/A converter 4, a comparator 5, and a successive comparator control circuit 10. The successive comparator control circuit 10 includes a maximum setting value register 11, a minimum value setting register 12, a successive comparator register 15, and a CPU (not shown in drawing) for performing A/D conversion processing. The maximum value register 11 and a minimum value setting register 12 are connected to a data bus 6 and an address bus 7.
FIG. 8 and FIG. 9 illustrates the A/D conversion processing implemented by the CPU in the successive comparator control circuit 10. The CPU sets the maximum value (Vmax register value) stored in maximum value setting register 11 as a temporary maximum value Vmax for the reference voltage (S201). The CPU sets a minimum value (Vmin register value) stored in the minimum value setting register 12, as a temporary minimum value Vmin for the reference voltage (S202). The CPU next processes these temporarily set maximum value Vmax and minimum value Vmin, adjusting them for use as reference voltage that can be output by the DAC4 (S203-S208). The CPU first of all decides whether or not the minimum value Vmin temporarily set in S202 and subtracted from the temporary maximum value Vmax set in S201, can be expressed as a power-of-two. The CPU in other words, decides whether the minimum value Vmin is divisible by two (S203 in FIG. 9). If the CPU decides the value is divisible by two (S203: Y), then the processing proceeds to S209 (FIG. 8). If the CPU decides the value is not divisible by two (S203: N) then a minimum increase/decrease width Vlsb determined by the conversion accuracy is added to the maximum value Vmax, and this summed value is then set as the maximum value Vmax (S204).
When the maximum value for a settable reference voltage is 5 V at a conversion accuracy of four bits, then the minimum increase/decrease width Vlsb at which the reference voltage can be increased or decreased is 0.625 V (=5 V/8). The CPU next decides whether the maximum values Vmax required via S204 have all become a “1” or not. The CPU in other words decides whether the upper limit of the settable maximum Vmax value has been reached (S205). If decided that the upper limit has not been reached (S205: N), then the processing returns to step S203, and a decision made on whether the value found from subtracting the minimum value Vmin from the maximum value Vmax found in S204 is divisible by two or not. If that value cannot be divided by two (S203: N), then the minimum increase/decrease width Vlsb is again added to the maximum value Vmax (S204). The maximum value Vmax is in other words repeatedly increased within a range that does not exceed the upper limit, and when the value found from subtracting the minimum value Vmin from the maximum value Vmax reaches a figure divisible by two (S203: Y), then the processing proceeds to S209.
If the CPU decides that the upper limit of the maximum value Vmax was reached (S205: Y), then a value found from subtracting the minimum increase/decrease width Vlsb from the minimum value Vmin temporarily set earlier in S202 (FIG. 8) is set as a new minimum value Vmin (S206). The CPU next decides whether the minimum values Vmin found in S206 are all zeroes or not in other words decides whether the lower limit for the settable minimum value Vmin was reached or not (S207). If decided that the lower limit was not reached (S207: N), then the CPU decides whether the maximum value Vmax, or in other words whether the value found from subtracting the minimum value Vmin found in S206 from the upper limit is divisible by two or not (S208). Here, if decided that value is not divisible by two (S208: N), then the minimum increase/decrease width Vlsb is once again subtracted from the minimum value Vmin (S206). In other words, if in a range not reaching the lower limit then the minimum value Vmin is repeatedly decreased, and when the value found from subtracting the minimum value Vmin from the maximum value Vmax reaches a value divisible by two (S208: Y), then the processing proceeds to S209.
In other words, the range of reference voltages outputted from DAC4 is set automatically based on the maximum value (Vmax register value) and minimum value (Vmin register value) input by the user.
The CPU next calculates the value obtained from summing the maximum value Vmax and the minimum value Vmin found in S203-S208 by two, or in other words, calculates the center value Vmid of the maximum value Vmax and the minimum value Vmin (S209). Next, (5 V+0 V)/2=2.5 V is calculated for the case where the maximum value Vmax for example is 5 V, and the minimum value Vmin is 0 V. The successive comparator control circuit 10 at this time outputs a digital output code for outputting reference voltages corresponding to the center value Vmid to the DAC4 as a control signal. The DAC4 in this way performs digital/analog (DA) conversion of the DAC control signal that was input, and outputs to the comparator 5 these reference voltages corresponding to center value Vmid.
The comparator 5 then compares the reference voltage (Vmid) outputted from the DAC4, with the analog input voltage Vin held by the S/H circuit 3, and outputs a signal corresponding to those comparison results to the successive comparator circuit 10. The CPU then decides whether the signal outputted from the comparator 5 shows comparison results such that the analog input voltage Vin is larger than the reference voltage (Vmid) or not (S210). If the comparison results show the analog input voltage Vin is larger than the reference voltage (Vmid) (S210: Y), then the reference voltage (Vmid) is set to a new minimum value Vmin (S211). If for example, the analog input voltage Vin is 3 V, and the reference voltage (Vmid) is 2.5 V, then the CPU decides that the analog input voltage Vin is larger than the reference voltage (Vmid) (S210:Y), and the 2.5 V of the reference voltage (Vmid) is set to a new minimum value Vmin (S211).
If the CPU decides that the comparison results show that the analog input voltage Vin is smaller than the reference voltage (Vmid) (S210:N), then the reference voltage (Vmid) is set to a new maximum value Vmax (S212). If for example, the analog input voltage Vin is 2 V, and the reference voltage (Vmid) is 2.5 V, then the CPU decides that the analog input voltage Vin is smaller than the reference voltage (Vmid) (S210:N), and the 2.5 V of the reference voltage (Vmid) is set to a new minimum value Vmin (S212).
The CPU next decides if the value found from subtracting the minimum value Vmin from the maximum value Vmax has become the minimum increase/decrease width Vlsb or not. In other words, the CPU decides whether the center value Vmid for the maximum value Vmax and minimum value Vmin is in a state that cannot be calculated (S213). For example, if the conversion accuracy (resolution) is 4 bits, maximum value Vmax is 5 V, the minimum value Vmin is 0 V, then the 0.625 V (=5V/8) becomes the minimum increase/decrease width Vlsb so that the CPU decides if the value found from subtracting minimum value Vmin from the maximum value Vmax is 0.625 V or not (S213).
If the CPU here decides that the center value Vmid cannot be calculated in this state (S213:N), then the process returns to S209 and center value Vmid is again calculated and a comparison made with that center value Vmid (S210). If for example, the analog input voltage Vin is 3 V, and the minimum value Vmin newly set previously in S211 is 2.5 V, then the CPU calculates that the center value Vmid=(5 V+2.5 V)/2=3.75 V (S209), and compares the analog input voltage of 3 V with the center value of 3.75 V (S210). The CPU therefore compares the analog input voltage Vin with the reference voltage (Vmid) as described above (S210), and based on those comparison results decides a new minimum value Vmin or maximum value Vmax (S211, S212) and calculates a new center value Vmid based on the minimum value Vmin or maximum value Vmax that were decided (S209). The CPU repeats this processing that compares the analog input voltage Vin with the reference voltage (Vmid) that is the new center value Vmid (S210).
Then, when the CPU decides the center value Vmid is in a state that cannot be calculated (S213:Y), it stores, a conversion value VSAR needed for finding the maximum value Vmax used in the final comparison in S213 in SAR15 (S214).
The range of the reference voltage (Vmid) required for making the comparison is set in this way based on the maximum value Vmax and minimum value Vmin set by the user, and set so as not to make comparisons with reference voltages (Vmid) outside this range.